1. Field of the Invention
The present invention relates to a semiconductor memory having a fuse circuit. It is particularly related to a semiconductor memory having a preferred configuration for continuous operation.
2. Description of the Related Art
A method of preparing spare memory cells in a semiconductor memory as countermeasures for defective memory cells and replacing the defective memory cells with the spare memory cells based on fuse information is employed.
A ‘fuse’ represents a logic state “0” or “1” determined by whether an electric conductor is conductive or disconnected; ‘fuse information’ means information for determining which address of memory cell is to be replaced with which spare memory cell; and a ‘fuse circuit’ means a circuit that provides fuse information for memory cells of the semiconductor memory.
The semiconductor memory having a fuse circuit is implemented by: a plurality of memory cell arrays; holding circuits, each being provided for each memory cell array and reading and holding fuse information; decision circuits, each being provided for each memory cell array and determining which address of memory cell is to be replaced with which spare memory cell based on the fuse information from corresponding holding circuit; and holding-controllers, which control reading and holding of the fuse information in the holding circuits. With an earlier semiconductor memory having such configuration, to begin with, a power supply completion signal POWERON, which is for notifying that an internal potential has been set once an electric power is supplied to the semiconductor memory, is transferred to the holding-controllers.
A holding-controller provides an initialization signal bFPUP to holding circuits once the power supply completion signal POWERON is transferred, and then after a specified period has passed, provides a determination signal FPUN to those holding circuits. The holding circuit initializes fuse information using the initialization signal bFPUP, reads the fuse information using the determination signal FPUN, and continues to hold that fuse information. The decision circuit determines which address of memory cell is to be replaced with which spare memory cell based on the fuse information from respective holding cell every time a memory cell is accessed. Accordingly, a defective memory cell among memory cells in respective memory cell arrays is replaced with a spare memory cell so as to serve as a normal memory cell.
In this manner, fuse information is read only once when power is supplied to the semiconductor memory, and is then held in that holding circuit. However, since the fuse information being held in the holding circuits may change from when it is read with an alpha particles soft error or unexplained disturbance noise, there is a problem where the decision circuit cannot accurately replace the defective memory cell with a spare memory cell, and the defective memory cell remains.
As a result, if such a semiconductor device is used for a system with which supplying power to such semiconductor memory is difficult, such as a device having to continuously run without even an instantaneous malfunction, or a communications network server, there is fear of causing critical failure of that system.
On the contrary, Japanese Patent Application Laid-open Hei 10-69798 discloses a semiconductor memory having a fuse circuit that is configured such as to correct an erroneously set state. The semiconductor memory disclosed in the Japanese Patent Application includes a fuse/latch circuit, which is implemented by three serially connected MOSFETs and an inverter; wherein the set state of the fuse/latch circuit, which is driven by pulse signals CLRNX, SETPX and SETPSP during an initializing sequence after power is supplied, is evaluated, and only the erroneously set fuse/latch circuit is correctly reset.
However, there is a problem with the semiconductor memory disclosed in the Japanese Patent Application where since evaluation of the set state of the fuse/latch circuit and correction of the erroneously set state are executed during the initializing sequence carried out immediately after power is supplied, the fuse information in an erroneous state after completion of the initializing sequence is not corrected.
As such, there is the problem with the semiconductor memory including the earlier fuse circuit where as long as power is not re-supplied when the fuse information is in an erroneously set state due to a malfunction, the erroneously set state cannot be corrected. As a result, there is fear of causing critical failure of a system with which re-supplying power to the earlier semiconductor memory is difficult. Particularly, there is a problem with the semiconductor memory disclosed in Japanese Patent Application where the fuse information in an erroneous state after completion of the initializing sequence carried out immediately after power is supplied is not corrected.